The present invention relates generally to bipolar transistors and, more particularly, to a process for forming a bipolar transistor with a raised extrinsic base in an integrated bipolar and complementary metal-oxide-semiconductor (BiCMOS) transistor circuit.
Transistors are used as either amplifying or switching devices in electronic circuits. In the first application, the transistor functions to amplify small ac signals. In the second application, a small current is used to switch the transistor between an xe2x80x9conxe2x80x9d state and an xe2x80x9coffxe2x80x9d state.
The bipolar transistor is an electronic device with two p-n junctions in close proximity. The bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions (the emitter-base and collector-base junctions) are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called xe2x80x9cbipolar-transistor action.xe2x80x9d
External leads can be attached to each of the three regions and external voltages and currents can be applied to the device using these leads. If the emitter and collector are doped n-type and the base is doped p-type, the device is an xe2x80x9cnpnxe2x80x9d transistor. Alternatively, if the opposite doping configuration is used, the device is a xe2x80x9cpnpxe2x80x9d transistor. Because the mobility of minority carriers (i.e., electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The silicon-germanium alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal-oxide-semiconductor (BiCMOS) technology uses a silicon-germanium base in the heterojunction bipolar transistor. In the high frequency (such as multi-GHz) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high speed wired and wireless communications. Silicon-germanium BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called xe2x80x9csystem on a chip.xe2x80x9d
For high performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation onto the extrinsic base. The ion implantation will cause damage, however, to the base region. Such damage ultimately may lead to degradation in device performance.
To avoid the implantation damage, a raised extrinsic base (REXT) is formed by depositing an extra layer of polycrystalline silicon (or silicon-germanium) atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be applied to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
1. Selective Epitaxy
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control.
U.S. Pat. No. 5,523,606 issued to Yamazaki discloses a process using selective epitaxy. Referring to FIGS. 1A and 1B, which correspond to portions of FIGS. 7C and 7E, respectively, of the ""606 patent, the extrinsic base poly silicon 21 is deposited before the intrinsic base 23 is deposited. Shown in FIG. 1A are silicon nitride film 15, silicon nitride side wall spacers 17, and semiconductor substrate 1. The films (not labeled) underneath the extrinsic base poly silicon 21 are etched away to form a cavity (or void) 22 of an over-hanging structure. The intrinsic base 23 is then selectively deposited, as shown in FIG. 1B, only inside the cavity 22 on the silicon and polysilicon exposed surface. See ""606 patent from column 8, line 53 to column 9, line 17. FIG. 1B also shows an n-type epitaxial collector layer 13. The approach disclosed in the ""606 patent avoids a CMP step, but has several drawbacks such as poor process control in filling the cavity 22 and stringent requirements for selective deposition conditions.
U.S. Pat. No. 5,620,908 was issued to Inoh et al. and titled xe2x80x9cManufacturing Method of Semiconductor Device Comprising BICMOS Transistor.xe2x80x9d Inoh et al. apply an approach similar to that disclosed by Yamazaki in the ""606 patent. Specifically, as illustrated in FIG. 6F of the ""908 patent and discussed in column 13 (specifically, at lines 24-26), Inoh et al. disclose a process that incorporates selective epitaxy and the step of etching an overhang to form a cavity.
2. CMP
The second type of process that can be applied to form a raised extrinsic base involves a CMP step. U.S. Pat. No. 5,015,594 was issued to Chu et al. and was assigned to the same assignee, International Business Machines Corporation, as the present invention. In their patent, titled xe2x80x9cProcess of Making BICMOS Devices Having Closely Spaced Device Regions,xe2x80x9d Chu et al. propose the formation of extrinsic base polysilicon by CMP. The isolation is achieved by thermal oxidation, however, which is not feasible in high performance devices due to the high temperature thermal process.
Y. C. Sun and J. Warnock disclose a process, in xe2x80x9cProcess for a High-Performance Bipolar-Based BICMOS,xe2x80x9d IBM Technical Disclosure Bulletin, vol. 35, no. 4B, pages 295-97 (September 1992), of forming a raised extrinsic base by CMP. The extrinsic base portion is formed in direct contact with the intrinsic base, however, without any etch stop. FIGS. 2A and 2B correspond to FIG. 1 of the article. With reference to FIGS. 2A and 2B, the extrinsic base polysilicon 21 is deposited directly above the intrinsic base region 5, which is also on the emitter opening region, without any interfacial films to stop the emitter opening etch 31 of the extrinsic base polysilicon 21. This process exhibits poor process control and, therefore, cannot yield good production control and cannot yield a highly reliable and reproducible bipolar device.
To stop the extrinsic polysilicon etch during formation of the emitter opening, an etch stop layer of dielectric materials such as oxide must be disposed underneath the extrinsic base polysilicon. This etch stop layer cannot cover the whole extrinsic base region, however, in order to form an electrical contact between the raised extrinsic base and the underneath base 25. Therefore, a need remains for a feasible approach to achieve those required features with CMOS circuit integration capability.
The deficiencies of the conventional methods show that a need still exists for an improved process of fabricating an HBT with a raised extrinsic base. To overcome the shortcomings of the conventional methods, a new process is provided. An object of the present invention is to form an HBT with a raised extrinsic base by CMP integrated in a CMOS circuit. A related object is to properly design the thickness of the emitter sacrifical plug and the CMOS gate stack so that the two structures have the same height across the entire wafer, with a flat top surface, to serve as a polish-stop layer for the formation of the raised extrinsic base as well as the isolation dielectric layer by CMP.
Another related object is to provide a fabrication process including a specific layer sequence and predetermined range of layer thicknesses for the HBT with a raised extrinsic base formed by CMP integrated in a CMOS circuit. Still another object of the present invention is to provide a process in which the CMOS gate dielectric stack is designed to form a flat surface aligned with the HBT emitter plug. Finally, a general object of the present invention is to provide a process sequence to form an entire BiCMOS circuit incorporating CMP process steps.
To achieve these and other objects, and in view of its purposes, the present invention provides a process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a complementary metal-oxide-semiconductor (CMOS) circuit with a gate. An intermediate semiconductor structure is provided having a CMOS area and a bipolar area. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack of silicon layer (referred to below as an emitter stack silicon layer) is deposited on, both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the emitter stack silicon layer from the CMOS area only such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP).
Two specific embodiments of the present invention are possible, depending upon the relative thicknesses of the various layers. In the first embodiment, the thickness of the emitter stack silicon layer is approximately equal to the thickness of the silicon gate of the CMOS area. The process then uses the base oxide as an etch stop such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the base oxide in the CMOS area.
In the second embodiment, the thickness of the emitter stack silicon layer plus the thickness of the intrinsic base layer is approximately equal to the thickness of the silicon gate of the CMOS area. The process then includes the step of etching to remove both the emitter stack silicon layer, the base oxide, and the intrinsic base layer from the CMOS area only, with a CMOS protective layer acting as an etch stop. This step assures that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the protective layer in the CMOS area.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.